1. Field of the Invention
This invention relates to an extracting transistor, that is to say a transistor in which intrinsic conductivity is reduced by carrier extraction.
2. Discussion of Prior Art
Before considering the prior art, semiconductor nomenclature and properties will be discussed. Transistor operation relies on electrical transport effects in semiconductor material, and, broadly speaking, there are three important conduction regimes: unsaturated extrinsic, saturated extrinsic and intrinsic, and these occur at low, intermediate and high temperature respectively. In the unsaturated extrinsic regime, there is insufficient thermal energy to ionise all impurities and the carrier concentration is temperature dependent because more impurities are ionised as temperature increases. Carriers are thermally activated from dopant impurities of a single species, i.e. donors or acceptors. Conduction is due substantially to one kind of carrier in one band, i.e. electrons in the conduction band or holes in the valence band but not both. The saturated extrinsic regime is similar, but occurs at higher temperatures at which virtually all impurities have become ionised but insufficient thermal energy is available to ionise significant numbers of valence band states to create electron-hole pairs: here the carrier concentration is largely independent of temperature.
In the intrinsic regime, conduction has a substantial contribution from thermal ionisation of valence band states producing both types of carrier, i.e. electron-hole pairs, in addition to carriers of one type activated from impurities. Conduction is due to both kinds of carrier in both bands, i.e. electrons in the conduction band and holes in the valence band. Conductivity varies with temperature in this regime because the electron-hole pair concentration is temperature dependent. There is an intervening transition region between the extrinsic and intrinsic regimes where conduction is partially extrinsic and partially intrinsic giving rise to more of one type of charge carrier than the other, i.e. majority carriers and minority carriers: it is at or near ambient temperature in Ge depending on doping. The onset temperature of intrinsic conduction depends on band gap and dopant concentration; it can occur below ambient temperature, as low as 150K in narrow gap semiconductors with low doping.
Materials such as Si and GaAs with a saturated extrinsic regime at ambient temperature are preferred for transistor applications despite their inferior mobility properties: this is because of the need for very low intrinsic carrier concentrations in the active regions of devices. Highly pure Ge is intrinsic at ambient temperature, and by analogy with this weakly doped Si is sometimes referred to wrongly as intrinsic, such as in PIN diodes where the high resistivity I (xe2x80x9cintrinsicxe2x80x9d) region is in fact extrinsic at ambient temperature. The purest Si currently available is more than an order of magnitude too impure to be intrinsic at ambient temperature.
Narrow band-gap semiconductors such as indium antimonide (InSb) have useful properties such as very low electron effective mass, very high electron mobility and high saturation velocity. These are potentially of great interest for ultra high speed transistor applications. InSb in particular is a promising material for fast, very low power dissipation transistors, because its electron mobility xcexce at low electric fields is nine times higher than that of GaAs and its saturation velocity vsat is more than five times higher, despite GaAs having better properties than Si in these respects. InSb is also predicted to have a large ballistic mean free path of over 0.5 xcexcm. This suggests that InSb has potential for high speed operation at very low voltages with consequent low power consumption, which would make it ideal for portable and high-density applications. Some of the properties of Silicon, GaAs and InSb at 295K (ambient temperature) are compared in Table 1 below.
Until recently, the potentially valuable properties of InSb have been inaccessible at ambient temperatures due to its low band-gap and consequently high intrinsic carrier concentration (xcx9c2xc3x971016 cmxe2x88x923), which is six and nine orders of magnitude above those of Si and GaAs respectively. This leads to InSb devices exhibiting high leakage currents at normal operating temperatures at or near ambient temperature of 295K, where the minority carrier concentration is much greater than the required value at normal doping levels. It was thought for many years that this was a fundamental problem which debarred InSb and other narrow band-gap materials from use in devices at ambient temperature and above.
The problem was however overcome to some extent in the invention the subject of U.S. Pat. No. 5,382,814: this patent discloses a non-equilibrium metal-insulator-semiconductor field effect transistor (MISFET) using the phenomena of carrier exclusion and extraction to reduce the intrinsic contribution to the carrier concentration below the equilibrium level. The MISFET is a reverse-biased p+p+pxe2x88x92n+ structure, where p denotes an InSb layer, p is a strained In1xe2x88x92xAlxSb layer (underlined p indicates wider band-gap than p), pxe2x88x92 indicates a weakly doped p-type region that is intrinsic at ambient operating temperature, and the + superscript indicates a high dopant concentration; these four layers define three junctions between adjacent layer pairs, i.e. p+p+, p+pxe2x88x92 and pxe2x88x92n+ junctions respectively. The active region of the device is the pxe2x88x92 region, and minority carriers are removed from it at the pxe2x88x92n+ junction acting as an extracting contact. The p+pxe2x88x92 junction is an excluding contact which inhibits re-introduction of these carriers. In consequence, under applied bias the minority carrier concentration falls in the active region, and the majority carrier concentration falls with it to a like extent to preserve charge neutrality. This reduces electron and hole concentrations by like amounts, which corresponds to a reduction in the intrinsic contribution to conductivity (electron-hole pairs) and takes the active region into an extrinsic-like regime.
International Patent Application No. WO 99/28975 published under the Patent Cooperation Treaty relates to a similar transistor which has a straightened channel to improve frequency response. These prior art extracting devices however suffer from the problem that they exhibit relatively high leakage current which increases power requirements and operating temperature.
It is an object of the invention to provide an alternative form of extracting transistor capable of operation with lower leakage current than the prior art.
An extracting transistor characterised in that:
a) it is a field effect transistor incorporating a conducting region consisting at least partly of a quantum well;
b) the quantum well is in an at least partially intrinsic conduction regime when the transistor is unbiased and at a normal operating temperature; and
c) it includes at least one junction which is biasable to reduce intrinsic conduction in the quantum well and confine charge carriers predominantly to one type only corresponding to an extrinsic saturated regime.
The invention provides the advantage that with transistor design in accordance with ordinary skill in the art of semiconductor device fabrication it is capable of reducing leakage current considerably: examples of the invention have exhibited an order of magnitude reduction in leakage current.
The transistor of the invention may contain an excluding junction for inhibiting minority carrier supply to the quantum well; it may be arranged for carrier exclusion at least partly by incorporation of an excluding heterojunction between two semiconductor materials of differing band-gap both wider than that of the quantum well.
The biasable junction may be an extracting junction for removal of carriers from the quantum well. It may be a heterojunction between indium antimonide and a semiconductor material having a wider band gap than indium antimonide: e.g. indium aluminium antimonide with x is in the range 0.10 to 0.5, preferably 0.15 to 0.2 or substantially 0.15.
The excluding junction may be a heterojunction between indium antimonide and a semiconductor material having a wider band gap than indium antimonide.
The quantum well material may have a band gap less than 0.4 eV, and may be indium antimonide.
In a preferred embodiment, the transistor of the invention includes a xcex4-doping layer arranged to be a dominant source of charge carriers for the quantum well. It may have an n+-pxe2x88x92-quantum wellxe2x80x94pxe2x88x92-p+-p+ diode structure or an n+-pxe2x88x92-quantum wellxe2x80x94pxe2x88x92-p+ diode structure.
The transistor of the invention may include a first excluding junction for inhibiting minority carrier supply to the quantum well and wide band-gap barrier layer to enhance such inhibiting effect. It may include a gate contact insulated from the active region by insulating material such as silicon dioxide or wide band-gap semiconductor material.
The transistor may alternatively include a gate contact deposited directly upon a surface of the active region and forming a Schottky contact thereto.
In one embodiment, the transistor includes source, gate and drain electrodes and a substrate contact, the biasable junction is a pn junction reverse biasable via the substrate contact to produce minority carrier extraction from the quantum well, and the substrate contact is connected externally to the source electrode.
The transistor may be p-channel with a p+-nxe2x88x92-quantum wellxe2x80x94nxe2x88x92-n+-n+ or a p+-pxe2x88x92-quantum wellxe2x80x94pxe2x88x92-n+-n+ structure, and include a xcex4-doping layer providing a predominant source of holes for the active region.
In another aspect, the invention provides a method of obtaining transistor operation characterised in that it includes the steps of:
a) providing an extracting field effect transistor incorporating:
i) source, gate and drain electrodes and a substrate contact and between such electrodes and contact a pn junction biasable via the substrate contact for minority carrier extraction;
ii) a conducting region consisting at least partly of a quantum well in an at least partially intrinsic conduction regime when the transistor is unbiased and at a normal operating temperature; and
iii) at least one junction which is biasable to reduce intrinsic conduction in the quantum well and confine charge carriers predominantly to one type only corresponding to an extrinsic saturated regime;
b) biasing the substrate contact to reverse bias the pn junction and to arrange for the substrate contact either to be at the same potential as the source electrode, or to be negative or positive with respect to the source electrode according to whether such electrode is associated with a p-type or n-type component of the pn junction.